P87C51MB2BA/02

Product Summary

The P87C51MB2BA/02 is an 8-bit microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2 features 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbytes of OTP and 2 Kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs or one enhanced UART and an SPI. Philips Semiconductors 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of program memory and 8Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits (ASICs).

Parametrics

P87C51MB2BA/02 absolute maximum ratings: (1)Operating temperature under bias: -55 to +125 ℃; (2)Storage temperature range: -65 to +150 ℃; (3)Voltage on EA/VPP pin to VSS: 0 to + 13.0 V; (4)Voltage on any other pin to VSS: -0.5 to VDD+0.5V V; (5)Maximum IOL per I/O pin: 20 mA; (6)Power dissipation (based on package heat transfer, not device power consumption): 1.5 W.

Features

P87C51MB2BA/02 features: (1)Extended features of the 51MX Core:; (2)23-bit program memory space and 23-bit data memory space linear program and data address range expanded to support; (3)up to 8 Mbytes each; (4)Program counter expanded to 23 bits; (5)Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation; (6)New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using; (7)pointers to access variables in different spaces.; (8)100% binary compatibility with the classic 80C51 so that existing code is completely reusable; (9)Up to 24 MHz CPU clock with 6 clock cycles per machine cycle; (10)96 Kbytes or 64 Kbytes of on-chip OTP; (11)3 Kbytes or 2 Kbytes of on-chip RAM; (12)Programmable Counter Array (PCA); (13)Two full-duplex enhanced UARTs; (14)Industry-standard Serial Peripheral Interface (SPI).

Diagrams